Ausgewählte Publikationen

1

H. Achatz. Extended 0/1 LP formulation for the scheduling problem in high-level synthesis. In Proc. 2nd European Design Automation Conf. (EURO-DAC '93), 1993. To appear.

2

W. Grass, C. Grobe, S. Lenk, and D. Tiedemann. Introducing structure into behavioral descriptions obtained from timing diagram specifications. In Proc. 19th EUROMICRO Conf., pages 581-588, 1993.

3

W. Grass, M. Mutz, and W. D. Tiedemann. High-level synthesis based on formal methods. In Proc. Workshop on Design Methodologies for Microelectronics and Signal Processing, Gliwice-Cracow, Poland, October 1993. To appear.

4

M. Mutz. Formal verification of sequential circuits with VERENA: A case study. In P. Prinetto and P. Camurati, editors, Correct Hardware Design and Methodologies. Elsevier Science Publishers B. V. (North-Holland), 1992.

5

W. D. Tiedemann. An approach to multi-paradigm controller synthesis from timing diagram specifications. In Proc. 1st European Design Automation Conf. (EURO-DAC '92), pages 522-527, 1992.